Hi,
Two questions about DRV8301 operation. Please kindly advice me. Thanks!
(1) If DRV8301's INL_A / INL_B / INL_C are floating with PWM_MODE value = 0, are GL_A / GL_B / GL_C kept high impedance and no PWM ouitput ?
(2) If the answer for above question is true, it means all of low-side FTE's GATE are floating. Besides, I input PWM into high-side FET's GATE. There are some deadband between these three PWM. Is it possible for this configuration to cause DRV8301 broken?
