DRV8825 and DRV8814 Internal Grounding Management

Hi TI Folks,

we have some questions on the ground management for the DRV8825 and DRV8814 as we are facing some noise coupling issue from Power GND to the Signal GND.

1. From the datasheet, both Pin14, Pin28 and the PPad are GND. How are they managed inside the chip?Is it possible to share the ground layout information inside the chip?

2. We would like to know if Pin14, Pin28 and PPad are all connected to a GND plane internally or Pin14, Pin28 and PPad are connected via GND traces.

3. Are there any noise management within the chip to ensure the digital logics are safe from the noise from noisy ground due to high current from the drivers?

Thanks in advance.

Regards,

Weiren