Part Number:DRV8840
Dear support Team
I found two different sources of information concerning those capacities in the datasheet – Revised December 2015 (should be the actual one)
On page 18 – 10.1 Layout Guideline – the following is written:
- "A low-ESR ceramic capacitor must be placed in between the CP1 and CP2 pins. TI recommends a value of 0.1μF rated for VM."
- "A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. TI recommends a value of 0.47μF rated for 16 V."
Now on page 14 – 8.2 Typical Application: I can found:
- 10nF instead of 100nF for the capacity between CP1 and CP2 as 100nF instead of 470nF for the capacity between VCP and WM
- On the CPG005 document – evaluation board – 10nF is also used between CP1 and CP2 and 100nF between VCP and VCMA but no resistor with 1M Ohm.
Please can you help me finding which version is correct, or what you will say, it's better?
Can you also help me concerning the value for the bulk capacity?
- In your provide document you are using 100µF – datasheet on page 14 as the CPG005.
- On page 17 – 9.1. Bulk Capacitance Sizing – you give a lot for factors which influence the value for this capacity but you didn’t give any equation to calculate the minimum and maximum capacity that should be use.
Can you provide me more information about it?
Many thanks for your help.
Best Regards,
Xavier