DRV8704 external FET negative Vgs over-voltage?

Hi,

Section 8.2.1 of the datasheet shows an example system specification with a supply voltage (VM) of 24V and referenced a FET which has a Vgs(max) of +/-20V.

My question is, how is the gate voltage managed for the upper FET which is turned off, as it's source will be close to GND.

I see the DRV8704EVM evaluation unit uses the very FET referenced.

Many thanks,

Bracken.