Ok, I'm getting unexpected responses from the DRV8301 on our board.
I see in the DRV reference manual:
"When nSCS is asserted high, any signals at the SCLK and SDI pins are ignored and SDO is forced into a high impedance state. When nSCS transitions from HIGH to LOW, SDO is enabled and the SDO response word loads into the shift register based on the previous SPI input word."
Does this mean I need to toggle chip select between each transaction? The above paragraph seems to indicate it...
All clarification appreciated!
Ed Averill